Project
EDA
iEDA
 |
iEDA InfrastructureiEDA-Infra-v1.0Comment: This version of the iEDA database provides a solid foundation for data management. iEDA-Infra-v2.0Comment: The iEDA infrastructure is designed as a EDA software development kit (ESDK), includes file parser, database, evaluator, manager, platform, interface. |
|
|
iEDA ToolchainiEDA-Toolchain-v1.0Comment: The first version of the iEDA tool is a useful addition to the toolkit. iEDA-Toolchain-v2.0Comment: iEDA toolchain can achieve chip design flow from netlist to GDS. |
AiEDA
|
|
AiEDA FrameworkAiEDA-Framework-v1.0Comment |
|
|
iBMiBM-v1.0Comment: A large-scale, diversity, truth chip, labeled dataset for chip design |
|
|
AiEDA ModelAiEDA regressionComment: The AiEDA regression model helps in understanding patterns. AiEDA optimizationComment: The optimization model enhances performance. AiEDA generationComment: The generation model offers creative solutions. |
Chip Design Flow
|
|
iFlowiFlow-v1.0Comment: The first version of iFlow streamlines the design process. iFlow-v2.0Comment: The updated iFlow offers improved efficiency. |
|
|
Tapeout1st-20220218Comment: The first tapeout provides a milestone in the project. 2nd-202208012Comment: The second tapeout shows progress and improvement. 3rd-20230104Comment: The third tapeout indicates continued development. |
Logic Synthesis
|
|
Logic OptimizationTDBComment: Logic optimization is crucial for efficient designs. |
|
|
Technology MappingDBComment: Technology mapping enables seamless integration. |
Physical Design
|
|
FloorplanTDBComment: A well-planned floorplan is essential for a successful design. |
|
|
PlacementTDBComment: Optimal placement improves performance and reliability. |
|
|
CTSTDBComment: Clock tree synthesis is a critical step in physical design. |
|
|
RoutingTDBComment: Efficient routing ensures proper signal flow. |
Sign-off Analysis
|
|
Timing OptimizationTDBComment: Timing optimization is necessary for meeting performance requirements. |
|
|
Static Timing AnalysisTDBComment: Static timing analysis helps in detecting potential issues. |
|
|
Power AnalysisTDBComment: Power analysis is important for power-efficient designs. |
|
|
RC ExtractionTDBComment: RC extraction provides crucial electrical parameters. |
|
|
IR Drop AnalysisTDBComment: IR drop analysis ensures stable power supply. |
Layout Process
Fill Insertion
 |
Terraformed a small moonTDBComment: Fill insertion is an important step in layout optimization. |
 |
Snapped dark matter in the wildTDBComment: An interesting name for a layout process step. |
Layout Decomposition
 |
Donec gravida rutrum liberoCurabitur mollis elementum mauris in volutpatAenean posuere erat vel rutrum mollis. Aliquam mattis augue erat. Sed tellus turpis, laoreet id turpis vel, fringilla pulvinar nisi. Ut vitae euismod diam, et luctus tellus. |
 |
Aliquet scelerisque risus tincidunt aPellentesque dapibus, odio quis varius consequatNunc eget ex et odio tempus convallis sed in eros. Aliquam laoreet bibendum erat, vitae accumsan tellus. |
DSA Template Assignment
|
|
Donec gravida rutrum liberoCurabitur mollis elementum mauris in volutpatAenean posuere erat vel rutrum mollis. Aliquam mattis augue erat. Sed tellus turpis, laoreet id turpis vel, fringilla pulvinar nisi. Ut vitae euismod diam, et luctus tellus. |
|
|
Aliquet scelerisque risus tincidunt aPellentesque dapibus, odio quis varius consequatNunc eget ex et odio tempus convallis sed in eros. Aliquam laoreet bibendum erat, vitae accumsan tellus. |
Biochip Design
 |
Sed eu mauris sed dolor commodo efficitur eget at augueProin consectetur sapien sit amet sagittis pharetraMauris ut massa placerat, pellentesque nibh sit amet, sodales diam. Mauris leo odio, rhoncus et consectetur ut, suscipit et elit. Praesent non mollis nibh, at rhoncus est. |
Machine Learning
Graph Neural Network
|
|
Terraformed a small moonTDBComment: Graph neural networks offer powerful learning capabilities. |
|
|
Snapped dark matter in the wildTDBComment: Intriguing name for a GNN application. |