An Open-Source Intelligent Physical Implementation Toolchain
iEDA is an open-source infrastructure for EDA. It provides a comprehensive toolkit for physical implementation of integrated circuits, including placement, routing, timing optimization, and DRC.
An Open-Source AI-Aided Design Library for Design-to-Vector
AiEDA is an open-source AI-aided design library that enables design-to-vector conversion for Electronic Design Automation. It leverages machine learning and deep learning techniques to optimize chip design processes.
Large Layout Model for Chip Design
Pre-training for chip layout design, building a large foundation model specialized for chip layout design, achieving chip layout generation without any manual intervention and EDA tools.
EDA infrastructure and RTL-GDS chip design tools: includes iNO, iFP, iPNP, iMP, iPL, iCTS, iTO, iRT, iIR, iSTA, iPA, iDRC and other tools.
Automated chip back-end design process, supporting 130/110/55/28nm processes, from RTL-GDS automated back-end design.
ASIC/FPGA process mapping tool, supporting the generation from AIG to Netlist.
Parsers required for EDA standard formats, including verilog, liberty, sdc, spef, sdf, vcd.
AI-aided design library, supporting data transformation, AI model training and application.
A collection of AI models designed for different EDA tasks.
A labeled EDA dataset, includes source data, process data, feature data, foundation data, vector data.